The present invention relates to a method for producing a self-aligned field effect transistor (FET) and, in particular, to a method for producing a self-aligned metal-semiconductor field effect transistor (MESFET) using III-IV compound semiconductors such as gallium arsenide (GaAs).
Gallium arsenide MESFET devices are useful in digital integrated circuits and high-frequency applications, e.g., in the microwave range. In such applications, it is necessary to improve the low noise property while reducing the gate resistance and the source-gate capacitance. In addition, it is desired to reduce the source resistance and increase the drain breakdown voltage. Attempts have been made to reduce the gate resistance and gate capacitance by reducing the gate length. For example, FIG. 2 shows a self-aligned N+-layer technology type field effect transistor produced using a dummy gate and multi-layer resist technology. In this structure, a semi-insulating gallium arsenide substrate 101b has an ion implanted active layer 102b therein. Through contact holes in an insulating layer 111b are formed source and drain contacts 116b and a Schottky gate contact 114b. However, using this technology, the oxide lift-off is difficult, and it is also difficult to reduce the gate length of the gate 114b less than 0.6 microns using conventional photolithographic and etching techniques. The capacitance between the gate and source is also undesirably large.
FIG. 3 shows another attempt to reduce the gate length by forming a self-aligned field effect transistor having side walls 119e. As shown in FIG. 3 a semi-insulating gallium arsenide substrate 101c has formed therein an active layer with silicon ion implanted ohmic contact regions 115c. An insulating region 111c is provided with source and drain contacts 116b being insulated from the gate 114c by side walls 119e. As with the structure shown in FIG. 2, it is difficult to reduce the gate length of the gate 114c to less than 0.6 microns. It is also difficult to control the process to prevent reaction from occurring between the ohmic contact region 116b and the rectifying junction of the gate 114c.
The structure shown in FIG. 4 has been developed in an attempt to reduce the length of the gate 114d to less than 0.5 microns using photolithography and etching. The structure shown in FIG. 4 has a semi-insulating gallium arsenide substrate 101d having an active layer 102d and ohmic contact regions 115d. Source and drain contact 116c contact the ohmic contact regions 115d through holes in the insulating layer 111d. Intrinsic side wall spacers 120 separate the gate 114d from the source and drain ohmic contact regions 115d. However, the capacitance of the gate-source through the insulating film is large and parasitic currents exist.
FIG. 5 shows a slant evaporation technique used in an attempt to reduce the gate length of the gate 114e to less than 0.5 microns. However, since it is difficult to control the slant evaporation, the reproducibility of the process in mass production is difficult.
Accordingly, it is still desired to provide a method for producing a self-aligned FET in particular a gallium arsenide MESFET, having a gate length less than 0,6 microns, for example, in the range of 0.3 to 0.5 microns, which is suitable for mass production and which achieves high reproducibility.